1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly relates to a bit line selection circuit of NAND flash memory devices.
2. Description of the Prior Art
A flash memory serves as a storage device which can be widely used in digital cameras, smart phones and other electronic devices. Demand for small size, high-capacity, fast access and low power consumption of a flash memory devices have increased.
A NAND-type flash memory is formed by a memory array configured with a plurality of NAND gate strings connected in a row direction. The NAND gate string is formed by a plurality of memory cells coupled in a row direction and selection transistors coupled to the two ends of the NAND gate string. One end of the NAND gate string is coupled to the bit line by one selection transistor, and the other end of the NAND gate string is coupled to the source line by the other selection transistor. Reading and programming of data is performed by a bit line coupled to the NAND gate string. For example, a flash memory is capable of improving the data programming speed.
FIG. 1 shows a bit line selection circuit of a conventional flash memory. The bit line selection circuit is configured with a pair of an even bit line BLe and an odd bit line BLo. The bit line selection circuit 300 includes a first selection part 310 comprising a selection transistor BLC for coupling the even bit line BLe or the odd bit line BLo to a sensor circuit and a second selection part 320 comprising bias transistors BIASe and BIASo for applying a bias VPRE to the even bit line BLe and the odd bit line BLo, and selection transistors BLSe and BLSo for coupling the even bit line BLe and the odd bit line BLo to the first selection part 310. In order to pre-charge a bias to the bit line when programming data or pre-charge an erasing voltage to a cell well when erasing data, the bias transistors BIASe and BIASo and the selection transistors BLSe and BLSo of the second selection part 320 are high voltage (HV) transistors with a thicker gate oxide film and longer gate length.
FIG. 2 shows a bit line selection circuit of K. Fukuda. Et al., in which the second selection part 320A of the bit line selection circuit 300A is formed by low voltage (LV) transistors. A relay part 330 which is formed by HV transistors is configured between the first selection part 310 and the second selection part 320A. The thickness of the gate oxide films of the transistors BIASe, BIASo, BLSe, and BLSo is a normal thickness, the gate length is shorter, and the gate oxide film is configured in the cell well. The transistor BLS of the relay part 330 is configured outside of the cell well, and is used when the LV transistors of the second selection part 320A are disconnected from the selection transistor BLC of the first selection part 310. When erasing data, the gates of the transistors of the second selection part 320A are floating, and the erasing voltage is increased by capacitance coupling between the gate and the cell well, so that the potential of the gate prevents the gate oxide films of the LV transistors from breaking down. Because the LV transistors in the second selection part 320A occupy a smaller layout area, small size of the memory is achieved.